Semiconductor device manufacturing method

ABSTRACT

A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of U.S. application Ser. No. 14/323,430, now U.S.Pat. No. 9,029,207, filed on Jul. 3, 2014, which is a divisional of U.S.application Ser. No. 13/565,026, filed on Aug. 2, 2012 (now U.S. Pat.No. 8,786,029, issued on Jul. 22, 2014). These prior US applications andthe present continuation application claimed the benefit of priority ofJapanese application 2011-170355, filed on Aug. 3, 2011.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device having asuper-junction structure and a manufacturing method thereof.

BACKGROUND

Conventionally, a super-junction structure is known as a structure forreducing the on-resistance without sacrificing the breakdown voltage ofa MOSFET (Metal Oxide Semiconductor Field Effect Transistor).Additionally, in the related art, there is known a super-junctionstructure which is formed by dry-etching an n-type siliconmonocrystalline substrate to form stripe-shaped trenches on thesubstrate at a specified interval and then filling the insides of thetrenches with filler epitaxial layers made of p-type siliconmonocrystals.

SUMMARY

The present disclosure provides a semiconductor device, including: ap-type semiconductor layer; n-type column regions arranged in a mutuallyspaced-apart relationship along a predetermined direction parallel to afront surface of the semiconductor layer, each of the n-type columnregions formed of a plurality of columnar thermal donors exhibiting ann-type property; a p-type column region of the semiconductor layerinterposed between the n-type column regions adjoining to each other,the n-type column regions configured to form a super-junction structurein the semiconductor layer in cooperation with the p-type column region;an n-type channel region selectively formed in a front surface portionof the semiconductor layer to make up a portion of the front surface ofthe semiconductor layer; a source region selectively formed in a frontsurface portion of the channel region to make up a portion of the frontsurface of the semiconductor layer, a conductivity type of the sourceregion being opposite to that of the channel region; a gate insulatorfilm formed on the front surface of the semiconductor layer; and a gateelectrode formed on the gate insulator film and opposite to the channelregion across the gate insulator film.

With this configuration, the columnar n-type column regions and thep-type column region extending in the thickness direction of thesemiconductor layer are arranged along the predetermined directionparallel to the front surface of the semiconductor layer, therebyforming a super-junction structure. With this super-junction structure,a depletion layer can be formed over the entire interface between then-type column region and the p-type column region to extend along theinterface (namely, in the thickness direction of the semiconductorlayer). As a result, it is possible to prevent local concentration ofelectric fields in the semiconductor layer, making it possible to reducethe on-resistance of the semiconductor device and to increase thebreakdown voltage of the semiconductor device.

In the present semiconductor device, the n-type column regions areformed of thermal donors. The thermal donors can be easily formed in theportions of the p-type semiconductor layer irradiated with H⁺ particlesby selectively irradiating H⁺ particles on the portions of thesemiconductor layer in which the thermal donors are to be formed andthen subjecting the irradiated portions to annealing. Therefore, ascompared with the related art, it is possible to form a super-junctionstructure in a short period of time and at low cost.

The regions in which the thermal donors are formed are determined by thestop positions of the injected H⁺ particles. Even if the annealing isperformed afterwards, the regions are not widened beyond the stoppositions of the H⁺ particles decided through the control of irradiationenergy of the H⁺ particles. As a result, the range of the n-type columnregions can be determined precisely by controlling the irradiationenergy of the H⁺ particles. This makes it possible to form the n-typecolumn regions as designed. Therefore, the super-junction structure canbe easily incorporated into a MOSFET of basic structure without havingto change the basic MOS structure and without affecting the MOSstructure. Due to the fact that the n-type column regions can be formedas designed, it is possible to prevent variations in specific resistanceamong the n-type column regions and to easily miniaturize the n-typecolumn regions. This helps miniaturize the semiconductor device.

In contrast, the conventional method of forming a super-junctionstructure suffers from a number of problems. For example, there isavailable a method in which a super-junction structure is formed byforming a trench in an n-type substrate and forming a p-type epitaxiallayer inside the trench. In this method, it is difficult to uniformlycontrol the depth of the trench by etching. This poses a problem in thatvariations are generated in the specific resistance of the p-typeepitaxial layer filled in the trench.

There is also available a method of forming a super-junction structurein which a step of injecting p-type impurities into the front surface ofan n-type substrate (epitaxial layer) and a step of causing an n-typeepitaxial layer to grow after the injection of impurities arealternately performed a plural number of times to thereby form pluralstages of p-type portions in the thickness direction of the n-typeepitaxial layer. The plural stages of p-type portions are activated byannealing, whereby all of the p-type portions are unified to form asuper-junction structure. In this method, it is necessary to alternatelyperform the impurity injection steps and the epitaxial growth steps anumber of times. This poses a problem in that the process time becomeslonger, thus leading to increased cost. In addition, the unified p-typeregions cannot be determined by the stop positions of the injectedp-type impurities. In other words, the p-type impurities activated byannealing are isotropically diffused with no regularity. This diffusionmakes it difficult to control the shape of the finally-formed p-typeregions.

The two conventional methods stated above have a common problem in thatthe super-junction structure has to be formed prior to forming the MOSstructure. Therefore, if the depth of the trench or the diffusion rangeof the p-type impurities differs from the designed one, the MOSstructure formed thereafter has to be changed from thepreviously-designed structure. According to the present semiconductordevice, as a means for solving the problems noted above, the n-typecolumn regions are formed by thermal donors. As compared with therelated art, it is therefore possible to easily form a super-junctionstructure as designed in a short period of time and at low cost.

In the present semiconductor device, the n-type column regions have aspecific resistance of, e.g., from 1.0 Ω·cm to 10.0 Ω·cm. The presentsemiconductor device may employ any one of a p-channel MOSFET and ann-channel MOSFET. In the present semiconductor device, the channelregion may be an n-type and the source region may be a p-type. Thepresent semiconductor device may further include: a p-channel MOSFETconfigured to induce a channel between the p-type source region and thep-type column region by applying a voltage to the gate electrode.

In this case, the semiconductor layer may include a p-type base regionformed in the direction of a rear surface of the semiconductor layerwith respect to the n-type column regions and the p-type column regionso as to extend below the n-type column regions and the p-type columnregion along the predetermined direction parallel to the front surfaceof the semiconductor layer. Accordingly, if a source voltage is appliedbetween the source region and the base region (between the source andthe drain) and a specified voltage is applied to the gate electrode in astate where the p-type base region (drain region) is grounded (namely,the p-type base region is kept at 0 V), it is possible to cause anelectric current to flow from the source region toward the base regionthrough the p-type column region in the thickness direction of thesemiconductor layer (in the vertical direction).

The p-channel MOSFET may be manufactured by, e.g., a semiconductordevice manufacturing method, including: preparing a p-type semiconductorlayer; forming an n-type channel region in a front surface portion ofthe p-type semiconductor layer by selectively injecting an n-typeimpurity into a front surface of the semiconductor layer and activatingthe n-type impurity through annealing, the n-type channel region makingup a portion of the front surface of the semiconductor layer; forming ap-type source region in a front surface portion of the channel region byselectively injecting a p-type impurity into the front surface of thesemiconductor layer and activating the p-type impurity throughannealing, the p-type source region making up a portion of the frontsurface of the semiconductor layer; forming a gate insulator film on thesurface of the semiconductor layer; forming a gate electrode on the gateinsulator film, the gate electrode opposite to a portion of the channelregion across the gate insulator film; and after formation of the gateelectrode, forming n-type column regions made of columnar thermal donorsexhibiting an n-type property by selectively irradiating H⁺ particles ona plurality of portions of the semiconductor layer mutually spaced apartalong a predetermined direction parallel to the front surface of thesemiconductor layer and inverting a conductivity type of the portions ofthe semiconductor layer irradiated with the H⁺ particles throughannealing, and, at the same time, forming p-type column regions havingthe same conductivity type as the conductivity type of the semiconductorlayer in portions interposed between the n-type column regions adjoiningto each other.

On the other hand, in the present semiconductor device, the channelregion may be a p-type and the source region may be an n-type. Thepresent semiconductor device may further include: an n-channel MOSFETconfigured to induce a channel between the n-type source region and then-type column region by applying a voltage to the gate electrode. Inthis case, the semiconductor layer may include an n-type base regionformed in the direction of a rear surface of the semiconductor layerwith respect to the n-type column regions and the p-type column regionso as to extend below the n-type column regions and the p-type columnregion along the predetermined direction parallel to the front surfaceof the semiconductor layer. Accordingly, if a drain voltage is appliedto between the source region and the n-type base region (drain region)(between the source and the drain) and a specified voltage is applied tothe gate electrode in a state where the n-type source region is grounded(namely, the n-type source region is kept at 0 V), it is possible tocause an electric current to flow from the base region toward the sourceregion through the n-type column region in the thickness direction ofthe semiconductor layer (in the vertical direction).

The n-channel MOSFET may be manufactured by, e.g., a semiconductordevice manufacturing method, including: preparing a p-type semiconductorlayer; forming an n-type source region in a front surface portion of thep-type semiconductor layer by selectively injecting an n-type impurityinto a front surface of the semiconductor layer and activating then-type impurity through annealing, the n-type source region making up aportion of the front surface of the semiconductor layer; forming a gateinsulator film on the surface of the semiconductor layer; forming a gateelectrode on the gate insulator film; and after formation of the gateelectrode, forming n-type column regions made of columnar thermal donorsexhibiting an n-type property by selectively irradiating H⁺ particles ona plurality of portions of the semiconductor layer mutually spaced apartalong a predetermined direction parallel to the front surface of thesemiconductor layer and inverting a conductivity type of the portions ofthe semiconductor layer irradiated with the H⁺ particles throughannealing, and, at the same time, forming a p-type channel region makingup a portion of the front surface of the semiconductor layer in aportion interposed between the n-type column regions adjoining to eachother so that the channel region can be partially opposite to the gateelectrode across the gate insulator film and forming a p-type columnregions below the channel region.

In the present semiconductor device, the n-type column region may be aregion formed in the direction of the rear surface of the semiconductorlayer with respect to the channel region so as to make contact with thechannel region. Alternatively, the n-type column region may be a regionformed in the direction of the rear surface of the semiconductor layerwith respect to the channel region in a spaced-apart relationship withthe channel region. Additionally, in the present semiconductor devicemanufacturing method, the annealing for the formation of thermal donorsmay be performed at a temperature of from 400 degrees C. to 450 degreesC.

The specific resistance of the n-type column regions made of thermaldonors grows smaller when the temperature increases until the annealingtemperature reaches 450 degrees C. or so. The specific resistancebecomes smallest at about 450 degrees C. Thereafter, if the temperatureexceeds 450 degrees C., the specific resistance grows larger as thetemperature increases and finally approaches the specific resistance ofthe semiconductor layer available before the irradiation of H⁺particles. In view of this, annealing is performed at a temperature offrom 400 degrees C. to 450 degrees C. in the present disclosure. Thismakes it possible to reduce the specific resistance of the n-type columnregions and to further reduce the on-resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic section view showing a semiconductor device(p-channel MOSFET) according to a first embodiment of the presentdisclosure.

FIGS. 2A, 2B and 2C are layout diagrams of n-type channel regions of thesemiconductor device shown in FIG. 1, FIG. 2A showing a stripe pattern,FIG. 2B showing a matrix pattern and FIG. 2C showing a zigzag pattern.

FIG. 3A is a view illustrating a step of a process for manufacturing thesemiconductor device shown in FIG. 1.

FIG. 3B is a view illustrating a step subsequent to the step shown inFIG. 3A.

FIG. 3C is a view illustrating a step subsequent to the step shown inFIG. 3B.

FIG. 3D is a view illustrating a step subsequent to the step shown inFIG. 3C.

FIG. 3E is a view illustrating a step subsequent to the step shown inFIG. 3D.

FIG. 4 is a graph representing the relationship between a specificresistance of a silicon turned into a thermal donor and an annealingtemperature.

FIG. 5 is a schematic section view showing a semiconductor device(n-channel MOSFET) according to a second embodiment of the presentdisclosure.

FIGS. 6A, 6B and 6C are layout diagrams of p⁻-type channel regions ofthe semiconductor device shown in FIG. 5, FIG. 6A showing a stripepattern, FIG. 6B showing a matrix pattern and FIG. 6C showing a zigzagpattern.

FIG. 7A is a view illustrating a step of a process for manufacturing thesemiconductor device shown in FIG. 5.

FIG. 7B is a view illustrating a step subsequent to the step shown inFIG. 7A.

FIG. 7C is a view illustrating a step subsequent to the step shown inFIG. 7B.

FIG. 7D is a view illustrating a step subsequent to the step shown inFIG. 7C.

FIG. 8 is a view showing a modified example of an n-type column regionof the semiconductor device shown in FIG. 1.

DETAILED DESCRIPTION

Certain embodiment of the present disclosure will now be described indetail with reference to the accompanying drawings.

<Embodiment of p-Channel MOSFET (First Embodiment)>

FIG. 1 is a schematic section view showing a semiconductor device 1(p-channel MOSFET) according to a first embodiment of the presentdisclosure. FIGS. 2A, 2B and 2C are layout diagrams of n-type channelregions 7 of the semiconductor device 1, FIG. 2A showing a stripepattern, FIG. 2B showing a matrix pattern and FIG. 2C showing a zigzagpattern.

The semiconductor device 1 includes a substrate 2 (having a thicknessof, e.g., from 100 μm to 700 μm) of p⁺-type silicon (having an acceptorconcentration of, e.g., from 10¹⁷ to 10¹⁹ atoms·cm⁻³). An epitaxiallayer 5 (semiconductor layer) made of p⁻-type silicon (having anacceptor concentration of, e.g., from 10¹⁵ to 10¹⁶ atoms·cm⁻³) is formedon a front surface 3 of the silicon substrate 2. The acceptorconcentration of the epitaxial layer 5 is lower than that of the siliconsubstrate 2. The thickness of the epitaxial layer 5 is, e.g., from 10 μmto 80 μm. A drain electrode 6 is formed on a rear surface 4 of thesilicon substrate 2. The drain electrode 6 is made of a metallicmaterial, e.g., Au (gold).

A plurality of n-type channel regions 7 (having an acceptorconcentration of, e.g., from 10¹⁵ to 10¹⁶ atoms·cm⁻³) is formed in afront surface portion of the epitaxial layer 5. Each of the channelregions 7 makes up a portion of a front surface 8 of the epitaxial layer5 (namely, the channel regions 7 are exposed at the front surface 8 ofthe epitaxial layer 5). As shown in FIG. 2A, the n-type channel regions7 are formed into a stripe pattern (extending in a directionperpendicular to FIG. 1) in which the channel regions 7 are arranged ata specified pitch. The layout of the n-type channel regions 7 is notlimited to a stripe pattern but may be a matrix pattern (row-columnpattern) in which the channel regions 7 are arranged at a specifiedpitch in a row direction and a column direction, as shown in FIG. 2B, ora zigzag pattern in which the channel regions 7 are alternately arrangedin the column direction, as shown in FIG. 2C.

P-type source regions 9 are formed in each of the n-type channel regions7 at opposing end portions in the traverse direction orthogonal to thelongitudinal direction (stripe direction) of the n-type channel regions7 in a spaced-apart relationship with the peripheral edge defining eachof the n-type channel regions 7. Each of the p-type source regions 9makes up a portion of the front surface 8 of the epitaxial layer 5. Thep-type source regions 9 are linearly formed to extend parallel to oneanother in the longitudinal direction. In the case of the matrix patternshown in FIG. 2B or the zigzag pattern shown in FIG. 2C, each of thep-type source regions 9 may be formed into, e.g., a ring shape, toextend along the peripheral edge of each of the n-type channel regions 7in a spaced-apart relationship with the peripheral edge.

N-type column regions 10 are formed in the epitaxial layer 5 below then-type channel regions 7. The n-type column regions 10 are formed inareas of the epitaxial layer 5 other than the areas directly below thep-type source regions 9. For example, if the n-type channel regions 7have the stripe pattern as shown in FIG. 2A, each of the n-type columnregions 10 is formed into a laminar shape (column shape in a sectionview) to extend through the epitaxial layer 5 from the front surface 8toward a rear surface 11 of the epitaxial layer 5 in the areas below thecentral portion of each of the n-type channel regions 7 interposedbetween the linear p-type source regions 9. The width W₁ of each of then-type column regions 10 in the transverse direction of the n-typechannel regions 7 is, e.g., from 2 μm to 8 μm. In the presentembodiment, the n-type column regions 10 are formed to make contact withthe n-type channel regions 7.

In the semiconductor device 1, the n-type column regions 10 are formedof thermal donors. The thermal donors refer to the portions in whichoxygen atoms and holes in the Si crystals are turned into donors whenthe epitaxial layer 5 (Si crystals) containing oxygen atoms is subjectedto annealing at about 450 degrees C. The thermal donors exhibit ann-type property in the p-type silicon. The existence of the thermaldonors can be observed by, e.g., ESR (Electron Paramagnetic Resonance).The specific resistance of the n-type column regions 10 formed of thethermal donors is, e.g., from 2 Ω·cm to 8 Ω·cm.

By forming the laminar n-type column regions 10, a super-junctionstructure is formed in the epitaxial layer 5. In the super-junctionstructure, the laminar n-type column regions 10 arranged at anappropriate pitch and laminar p⁻-type column regions 12 having the sameconductivity type as that of the epitaxial layer 5 are alternatelyarranged along a predetermined direction parallel to the front surface 8of the epitaxial layer 5.

The region of the epitaxial layer 5 existing in the direction of thesilicon substrate 2 with respect to the n-type column regions 10 and thep⁻-type column regions 12 and making contact with the front surface 3 ofthe silicon substrate 2 is a p⁻-type base region 13. The p⁻-type baseregion 13 extends below the n-type column regions 10 and the p⁻-typecolumn regions 12 in parallel with the front surface 8 of the epitaxiallayer 5. The p⁻-type base region 13 existing between the n-type columnregions 10 and the p⁺-type silicon substrate 2 prevents the n-typecolumn regions 10 and the p⁺-type silicon substrate 2 from makingcontact with each other. The depth D₁ of the n-type column regions 10(the distance from the front surface 8 of the epitaxial layer 5 to thedeepest portion of the n-type column regions 10) is, e.g., from 25 μm to70 μm. The deepest portion of the n-type column regions 10 is located atpositions spaced from the front surface 3 of the silicon substrate 2.

In the case where the n-type channel regions 7 have a matrix pattern, asshown in FIG. 2B, or a zigzag pattern, as shown in FIG. 2C, each of then-type column regions 10 may be formed in the area below the centralportion of each of the n-type channel regions 7 surrounded by each ofthe ring-shaped p-type source regions 9 so as to have a column shapeextending from each of the n-type channel regions 7 toward the siliconsubstrate 2.

On the front surface 8 of the epitaxial layer 5, there is formed a gateinsulator film 14 made of, e.g., SiO₂ (silicon oxide). A gate electrode15 is formed on the gate insulator film 14.

The gate electrode 15 is formed into a stripe shape to extend along then-type channel regions 7 having a stripe shape. The gate electrode 15 isopposite to, across the gate insulator film 14, a portion of each of then-type channel regions 7 exposed between the peripheral edge of each ofthe n-type channel regions 7 and a p-type source region 9. The gateelectrode 15 is made of, e.g., polysilicon containing an impurity at ahigh concentration. In the event that the n-type channel regions 7 havethe matrix pattern as shown in FIG. 2B, the gate electrode 15 may beformed into a lattice shape so as to surround each of the n-type channelregions 7.

An inter-layer insulator film 16 made of, e.g., SiO₂, is formed on theepitaxial layer 5 so as to cover the gate electrode 15. A plurality ofcontact holes 17 is formed in the inter-layer insulator film 16 and thegate insulator film 14. Each of the p-type source regions 9 and each ofthe n-type channel regions 7 are partially exposed in each of thecontact holes 17. A source electrode 18 is formed on the inter-layerinsulator film 16. The source electrode 18 makes contact with all of thep-type source regions 9 and all of the n-type channel regions 7 througheach of the contact hole 17. In other words, the source electrode 18serves as a common wiring line with respect to all of the unit cells.The source electrode 18 is made of a metallic material, e.g., Al(aluminum).

FIGS. 3A through 3E are views showing steps of a process formanufacturing the semiconductor device 1 shown in FIG. 1. In order tomanufacture the semiconductor device 1, as shown in FIG. 3A, Si crystalsare caused to grow on the front surface 3 of the silicon substrate 2 byan epitaxial growth method such as CVD (Chemical Vapor Deposition), LPE(Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy), while injectinga p-type impurity, e.g., B (boron). As a result, a p⁻-type epitaxiallayer 5 is formed on the silicon substrate 2.

Next, a hard mask 19 is formed so as to selectively cover the portionsof the epitaxial layer 5 other than the portions in which the n-typechannel regions 7 are to be formed. Then, an n-type impurity, e.g., P(phosphor), is accelerated toward the front surface 8 of the epitaxiallayer 5 exposed from the hard mask 19, thereby injecting the n-typeimpurity into the front surface 8 (ion injection). Subsequently, theepitaxial layer 5 is subjected to annealing at a temperature of, e.g.,from 1000 degrees C. to 1150 degrees C. Thus, the n-type impurityinjected into the front surface 8 of the epitaxial layer 5 is activatedto form the n-type channel regions 7.

Next, as shown in FIG. 3B, a hard mask 20 is formed so as to selectivelycover the portions of the epitaxial layer 5 other than the portions inwhich the p-type source regions 9 are to be formed. Then, a p-typeimpurity is accelerated toward the front surface 8 of the epitaxiallayer 5 exposed from the hard mask 20, thereby injecting the p-typeimpurity into the front surface 8 (ion injection). Subsequently, theepitaxial layer 5 is subjected to annealing at a temperature of, e.g.,from 800 degrees C. to 950 degrees C. Thus, the p-type impurity injectedinto the front surface 8 of the epitaxial layer 5 is activated to formthe p-type source regions 9.

Next, as shown in FIG. 3C, the front surface 8 of the epitaxial layer 5is subjected to thermal oxidation at a temperature of, e.g., from 800degrees C. to 1080 degrees C., thereby forming a gate insulator film 14that covers the entirety of the front surface 8 of the epitaxial layer5. Then, polysilicon is deposited on the epitaxial layer 5 by, e.g.,CVD, while injecting an impurity (any one of n-type and p-typeimpurities). Thereafter, unnecessary portions of the depositedpolysilicon (other than the portions to become the gate electrodes 15)are removed by dry etching, thereby forming the gate electrodes 15.

Subsequently, an inter-layer insulator film 16 made of, e.g., SiO₂ isdeposited on the epitaxial layer 5 by, e.g., CVD. Contact holes 17 areformed by simultaneously patterning the inter-layer insulator film 16and the gate insulator film 14.

Next, as shown in FIG. 3D, a thick resist mask 21 (having a thicknessof, e.g., from 5 μm to 20 μm) made of a photoresist is formed so as toselectively cover the portions of the epitaxial layer 5 other than theportions in which the n-type column regions 10 are to be formed. Then,H⁺ particles are accelerated toward the front surface 8 of the epitaxiallayer 5 exposed from the resist mask 21, thereby irradiating H⁺particles on the front surface 8 (H⁺ irradiation). The H⁺ irradiation isperformed in multiple stages while changing the acceleration energy ofthe H⁺ particles in a step-by-step manner. For example, the H⁺irradiation may be performed between 5 MeV and 10 MeV, while reducingthe energy from a high level to a low level in a step-by-step manner (intwo through five steps). This makes it possible to irradiate H⁺particles into the area extending from a bottom portion to a frontsurface portion of the epitaxial layer 5. After the H⁺ irradiation, thethick resist mask 21 is peeled off.

Next, as shown in FIG. 3E, the epitaxial layer 5 is subjected toannealing at a temperature of, e.g., from 400 degrees C. to 450 degreesC. Thus, the H⁺ particles included in the epitaxial layer 5 by the H⁺irradiation become promoters, thereby turning the oxygen atoms and holesin the epitaxial layer 5 (Si crystals) into donors. The portionsirradiated with the H⁺ particles become thermal donors exhibiting ann-type property. As a result, there are formed n-type column regions 10made of the thermal donors. At the same time, there are formed p⁻-typecolumn regions 12 and a p⁻-type base region 13 having the sameconductivity type (p⁻-type) as that of the epitaxial layer 5.

Thereafter, a source electrode 18 is formed by depositing Al (metallicmaterial) at a sputtering temperature of, e.g., 500 degrees C. to 600degrees C. A drain electrode 6 is formed by depositing Au (metallicmaterial) at a sputtering temperature of, e.g., 380 degrees C. to 420degrees C. The semiconductor device 1 shown in FIG. 1 is obtainedthrough the steps set forth above.

In the semiconductor device 1 (p-channel MOSFET), if a source voltage isapplied between the source electrode 18 and the drain electrode 6(between the source and the drain), and a specified voltage is appliedto the gate electrodes 15 in a state where the drain electrode 6 isgrounded (namely, the p⁻-type base region 13 is kept at 0 V), it ispossible to cause an electric current to flow from the p-type sourceregions 9 toward the p⁻-type base region 13 through the p⁻-type columnregions 12 in the thickness direction of the epitaxial layer 5 (in thevertical direction).

According to the semiconductor device 1 described above, the columnarn-type column regions 10 and the p⁻-type column regions 12 extending inthe thickness direction of the epitaxial layer 5 are alternatelyarranged along a direction parallel to the front surface 8 of theepitaxial layer 5, thereby forming a super-junction structure. With thissuper-junction structure, a depletion layer can be formed over theentire interface between the columnar n-type column region 10 and thep⁻-type column region 12 to extend along the direction of the interface(namely, in the thickness direction of the epitaxial layer 5). As aresult, it is possible to prevent local concentration of electric fieldsin the epitaxial layer 5, making it possible to reduce the on-resistanceof the semiconductor device 1 and to increase the breakdown voltage ofthe semiconductor device 1.

In the semiconductor device 1, the n-type column regions 10 are formedof thermal donors. As set forth above, the thermal donors can be easilyformed in the portions of the p⁻-type epitaxial layer 5 irradiated withH⁺ particles, by selectively irradiating H⁺ particles on the portions ofthe epitaxial layer 5 in which the thermal donors are to be formed (thestep shown in FIG. 3D) and then subjecting the irradiated portions toannealing (the step shown in FIG. 3E). Therefore, as compared with therelated art, it is possible to form a super-junction structure in ashort period of time and at low cost.

The regions (the n-type column regions 10) in which the thermal donorsare formed are determined by the stop positions of the injected H⁺particles. Even if the annealing is performed afterwards, the regions(the n-type column regions 10) are not widened beyond the stop positionsof the H⁺ particles decided through the control of irradiation energy ofthe H⁺ particles. As a result, the range of the n-type column regions 10can be determined precisely by controlling the irradiation energy of theH⁺ particles. This makes it possible to form the n-type column regions10 as designed. Therefore, the super-junction structure can be easilyincorporated into a MOSFET of basic structure without having to changethe basic MOS structure and without affecting the MOS structure. Due tothe fact that the n-type column regions 10 can be formed as designed, itis possible to prevent variations in specific resistance among then-type column regions 10 and to easily miniaturize the n-type columnregions 10. This helps miniaturize the semiconductor device 1.

In contrast, the conventional method of forming a super-junctionstructure suffers from a number of problems. For example, there isavailable a method in which a super-junction structure is formed byforming a trench in an n-type substrate and forming a p-type epitaxiallayer inside the trench. In this method, it is difficult to uniformlycontrol the depth of the trench by etching. This poses a problem in thatvariations are generated in the specific resistance of the p-typeepitaxial layer filled in the trench.

There is also available a method of forming a super-junction structurein which a step of injecting p-type impurities into the front surface ofan n-type substrate (epitaxial layer) and a step of causing an n-typeepitaxial layer to grow after the injection of impurities arealternately performed a plural number of times to thereby form pluralstages of p-type portions in the thickness direction of the n-typeepitaxial layer. The plural stages of p-type portions are activated byannealing, whereby all of the p-type portions are unified to form asuper-junction structure. In this method, it is necessary to alternatelyperform the impurity injection steps and the epitaxial growth steps anumber of times. This poses a problem in that the process time becomeslonger, thus leading to increased cost. In addition, the unified p-typeregions cannot be determined by the stop positions of the injectedp-type impurities. In other words, the p-type impurities activated byannealing are isotropically diffused with no regularity. This diffusionmakes it difficult to control the shape of the finally-formed p-typeregions.

The two conventional methods stated above have a common problem in thatthe super-junction structure has to be formed prior to forming the MOSstructure. Therefore, if the depth of the trench or the diffusion rangeof the p-type impurities differs from the designed one, the MOSstructure formed thereafter has to be changed from thepreviously-designed structure.

According to the present semiconductor device 1, as a means for solvingthe problems noted above, the n-type column regions 10 are formed bythermal donors. As compared with the related art, it is thereforepossible to easily form a super-junction structure as designed in ashort period of time and at low cost.

Referring to FIG. 4, the specific resistance of the n-type columnregions 10 made of thermal donors grows smaller when the annealingtemperature increases until the annealing temperature reaches 450degrees C. or so. The specific resistance becomes smallest at about 450degrees C. Thereafter, if the temperature exceeds 450 degrees C., thespecific resistance grows larger as the temperature increases andfinally approaches the specific resistance of the epitaxial layer 5available before the irradiation of H⁺ particles. In view of this,annealing is performed at a temperature of from 400 degrees C. to 450degrees C. in the step shown in FIG. 3E. This makes it possible toreduce the specific resistance of the n-type column regions 10 and tofurther reduce the on-resistance.

<Embodiment of n-Channel MOSFET (Second Embodiment)>

FIG. 5 is a schematic section view showing a semiconductor device 31(n-channel MOSFET) according to a second embodiment of the presentdisclosure. FIGS. 6A, 6B and 6C are layout diagrams of channel regions39 of the semiconductor device 31 shown in FIG. 5, FIG. 6A showing astripe pattern, FIG. 6B showing a matrix pattern and FIG. 6C showing azigzag pattern.

The semiconductor device 31 includes an n⁺-type silicon substrate 32(having a thickness of, e.g., from 500 μm to 650 μm). An epitaxial layer35 (semiconductor layer) made of silicon is formed on a front surface 33of the silicon substrate 32. A drain electrode 36 is formed on a rearsurface 34 of the silicon substrate 32. The drain electrode 36 is madeof a metallic material, e.g., Au (gold).

The epitaxial layer 35 includes an n⁻-type base layer 37 (base region)formed to make contact with the front surface 33 of the siliconsubstrate 32 and having a lower concentration than the silicon substrate32. The epitaxial layer 35 also includes a p⁻-type drift layer 38 formedon the n⁻-type base layer 37 and having a lower concentration than thesilicon substrate 32. The total thickness of the epitaxial layer 35 is,e.g., from 10 μm to 80 μm. The thickness of the n⁻-type base layer 37 issmaller than the thickness of the p⁻-type drift layer 38.

A plurality of p⁻-type channel regions 39 is formed in a front surfaceportion of the epitaxial layer 35 (the p⁻-type drift layer 38). Each ofthe p⁻-type channel regions 39 makes up a portion of the front surface40 of the epitaxial layer 35 (namely, the p⁻-type channel regions 39 areexposed at the front surface 40 of the epitaxial layer 35). As shown inFIG. 6A, the p⁻-type channel regions 39 are formed into a stripe pattern(extending in a direction perpendicular to FIG. 5) in which the p⁻-typechannel regions 39 are arranged at a specified pitch. The layout of thep⁻-type channel regions 39 is not limited to a stripe pattern but may bea matrix pattern (row-column pattern) in which the p⁻-type channelregions 39 are arranged at a specified pitch in a row direction and acolumn direction, as shown in FIG. 6B, or a zigzag pattern in which thep⁻-type channel regions 39 are alternately arranged in the columndirection, as shown in FIG. 6C.

N-type source regions 41 are formed in each of the p⁻-type channelregions 39 at opposing end portions in the traverse direction orthogonalto the longitudinal direction (stripe direction) of the p⁻-type channelregions 39 in a spaced-apart relationship with the peripheral edgedefining each of the p⁻-type channel regions 39. Each of the n-typesource regions 41 makes up a portion of the front surface 40 of theepitaxial layer 35. The n-type source regions 41 are linearly formed toextend parallel to one another in the longitudinal direction. In thecase of the matrix pattern shown in FIG. 6B or the zigzag pattern shownin FIG. 6C, each of the n-type source regions 41 may be formed into,e.g., a ring shape, to extend along the peripheral edge of each of thep⁻-type channel regions 39 in a spaced-apart relationship with theperipheral edge.

P⁻-type column regions 42 having the same conductivity type as that ofthe epitaxial layer 35 are formed in the epitaxial layer 35 below thep⁻-type channel regions 39 of the epitaxial layer 35. The p⁻-type columnregions 42 are formed to overlap with areas below partial portions ofthe n-type source regions 41 of the epitaxial layer 35. For example, ifthe p⁻-type channel regions 39 have the stripe pattern as shown in FIG.6A, each of the p⁻-type column regions 42 is formed into a laminar shape(column shape in a section view) to extend through the epitaxial layer35 from the front surface 40 toward the rear surface 43 in the areasbelow the partial portion of the linear n-type source regions 41 and thearea below the central portion of each of the p⁻-type channel regions 39interposed between the n-type source regions 41. The width W₂ of each ofthe p⁻-type column regions 42 in the transverse direction of the p⁻-typechannel regions 39 is, e.g., from 2 μm to 8 μm. In the presentembodiment, the p⁻-type column regions 42 are formed to make contactwith the p⁻-type channel regions 39.

In the epitaxial layer 35, n-type column regions 44 are formed betweenthe p⁻-type column regions 42 and are arranged at a predetermined pitch.When seen in a plan view, the n-type column regions 44 overlap with theperipheral edge portions of the p⁻-type channel regions 39. In someembodiment, the n-type column regions 44 may be formed to surround thep⁻-type column regions 42. The n-type column regions 44 are formed ofthermal donors. The thermal donors refer to the portions in which oxygenatoms and holes in the Si crystals are turned into donors when theepitaxial layer 35 (Si crystals) containing oxygen atoms is subjected toannealing at about 450 degrees C. The thermal donors exhibit an n-typeproperty in the p-type silicon. The existence of the thermal donors canbe observed by, e.g., ESR or the like. The specific resistance of then-type column regions 44 formed of the thermal donors is, e.g., from 2Ω·cm to 8 Ω·cm.

In the semiconductor device 31, there is formed a super-junctionstructure in which the p⁻-type column regions 42 having the sameconductivity type as that of the epitaxial layer 35, and the n-typecolumn regions 44 interposed between the mutually-adjoining p⁻-typecolumn regions 42 are alternately arranged along a direction parallel tothe front surface 40 of the epitaxial layer 35.

The region of the epitaxial layer 35 existing in the direction of thesilicon substrate 32 with respect to the n-type column regions 44 andthe p⁻-type column regions 42 and making contact with the front surface33 of the silicon substrate 32 is an n⁻-type base layer 37. The n⁻-typebase layer 37 extends below the n-type column regions 44 and the p⁻-typecolumn regions 42. The n⁻-type base layer 37 existing between the n-typecolumn regions 44 and the n⁺-type silicon substrate 32 prevents thep⁻-type column regions 42 and the n⁺-type silicon substrate 32 frommaking contact with each other.

In the case where the p⁻-type channel regions 39 have a matrix pattern,as shown in FIG. 6B, or a zigzag pattern, as shown in FIG. 6C, each ofthe p⁻-type column regions 42 may be formed in the area below thecentral portion of each of the p⁻-type channel regions 39 surrounded byeach of the ring-shaped n-type source regions 41 so as to have a columnshape extending from each of the p⁻-type channel regions 39 toward thesilicon substrate 32.

On the front surface 40 of the epitaxial layer 35, there is formed agate insulator film 45 made of, e.g., SiO₂ (silicon oxide). A gateelectrode 46 is formed on the gate insulator film 45.

The gate electrode 46 is formed into a stripe shape to extend along thep⁻-type channel regions 39 having a stripe shape. The gate electrode 46is opposite to, across the gate insulator film 45, a portion of each ofthe p⁻-type channel regions 39 exposed between the peripheral edge ofeach of the p⁻-type channel regions 39 and an n-type source regions 41.The gate electrode 46 is made of, e.g., polysilicon containing animpurity at a high concentration. In the event that the p⁻-type channelregions 39 have the matrix pattern as shown in FIG. 6B, the gateelectrode 46 may be formed into a lattice shape so as to surround eachof the p⁻-type channel regions 39.

An inter-layer insulator film 47 made of, e.g., SiO₂, is formed on theepitaxial layer 35 so as to cover the gate electrode 46. A contact hole48 is formed in the inter-layer insulator film 47 and the gate insulatorfilm 45. Each of the n-type source regions 41 and each of the p⁻-typechannel regions 39 are partially exposed in the contact hole 48. Asource electrode 49 is formed on the inter-layer insulator film 47. Thesource electrode 49 makes contact with all of the n-type source regions41 and all of the p⁻-type channel regions 39 through the contact hole48. In other words, the source electrode 49 serves as a common wiringline with respect to all of the unit cells. The source electrode 49 ismade of a metallic material, e.g., Al (aluminum).

FIGS. 7A through 7D are views showing steps of a process formanufacturing the semiconductor device 31 shown in FIG. 5. In order tomanufacture the semiconductor device 31, as shown in FIG. 7A, Sicrystals are caused to grow on the front surface 33 of the siliconsubstrate 32 by an epitaxial growth method such as CVD, LPE or MBE,while injecting an n-type impurity, e.g., P (phosphor). Then, the Sicrystals are caused to grow while injecting a p-type impurity such as B(boron). As a result, an epitaxial layer 35 including an n⁻-type baselayer 37 and a p⁻-type drift layer 38 is formed on the silicon substrate32.

Next, a hard mask 50 is formed so as to selectively cover the portionsof the epitaxial layer 35 other than the portions in which n-type sourceregions 41 are to be formed. Then, an n-type impurity is acceleratedtoward the front surface 40 of the epitaxial layer 35 exposed from thehard mask 50, thereby injecting the n-type impurity into the frontsurface 40 (ion injection). Subsequently, the epitaxial layer 35 issubjected to annealing at a temperature of, e.g., from 800 degrees C. to900 degrees C. Thus, the n-type impurity injected into the front surface40 of the epitaxial layer 35 is activated to form n-type source regions41.

Next, as shown in FIG. 7B, the front surface 40 of the epitaxial layer35 is subjected to thermal oxidation, thereby forming a gate insulatorfilm 45 that covers the entirety of the front surface 40 of theepitaxial layer 35. Then, polysilicon is deposited on the epitaxiallayer 35 by, e.g., CVD, while injecting an impurity (any one of n-typeand p-type impurities). Thereafter, unnecessary portions of thedeposited polysilicon (other than the portions to become gate electrodes46) are removed by dry etching, thereby forming gate electrodes 46.

Subsequently, an inter-layer insulator film 47 made of, e.g., SiO₂ isdeposited on the epitaxial layer 35 by, e.g., CVD. Contact holes 48 areformed by simultaneously patterning the inter-layer insulator film 47and the gate insulator film 45.

Next, as shown in FIG. 7C, a thick resist mask 51 (having a thicknessof, e.g., from 5 μm to 20 μm) made of a photoresist is formed on therear surface 34 of the silicon substrate 32 so as to selectively coverthe portions of the epitaxial layer 35 other than the portions in whichn-type column regions 44 are to be formed. Then, H⁺ particles areaccelerated toward the rear surface 34 of the silicon substrate 32exposed from the resist mask 51, thereby irradiating H⁺ particles on therear surface 34 (H⁺ irradiation). The H⁺ irradiation is performed inmultiple stages while changing the acceleration energy of the H⁺particles in a step-by-step manner. For example, the H⁺ irradiation isperformed between 5 MeV and 10 MeV, while reducing the energy from ahigh level to a low level in a step-by-step manner (in two through fivesteps). This makes it possible to irradiate H⁺ particles into the areaextending from a bottom portion to a front surface portion of theepitaxial layer 35. After the H⁺ irradiation, the thick resist mask 51is peeled off.

Next, as shown in FIG. 7D, the epitaxial layer 35 is subjected toannealing at a temperature of, e.g., from 400 degrees C. to 450 degreesC. Thus, the H⁺ particles included in the epitaxial layer 35 by the H⁺irradiation become promoters, thereby turning the oxygen atoms and holesin the epitaxial layer 35 (Si crystals) into donors. The portionsirradiated with the H⁺ particles become thermal donors exhibiting ann-type property. As a result, there are formed n-type column regions 44made of the thermal donors. At the same time, there are formed p⁻-typecolumn regions 42 and p⁻-type channel regions 39 having the sameconductivity type (p⁻-type) as that of the epitaxial layer 35.

Thereafter, a source electrode 49 is formed by depositing Al (metallicmaterial) at a sputtering temperature of, e.g., 500 degrees C. to 600degrees C. A drain electrode 36 is formed by depositing Au (metallicmaterial) at a sputtering temperature of, e.g., 380 degrees C. to 450degrees C. The semiconductor device 31 shown in FIG. 5 is obtainedthrough the steps set forth above.

In the semiconductor device 31 (n-channel MOSFET), if a drain voltage isapplied between the source electrode 49 and the drain electrode 36(between the source and the drain) and a specified voltage is applied tothe gate electrodes 46 in a state where the source electrode 49 isgrounded (namely, the n-type source regions 41 are kept at 0 V), it ispossible to cause an electric current to flow from the n⁻-type baselayer 37 toward the n-type source regions 41 through the n-type columnregions 44 in the thickness direction of the epitaxial layer 35 (in thevertical direction).

According to the semiconductor device 31 described above, like thesemiconductor device 1 of the first embodiment, there is formed asuper-junction structure including the n-type column regions 44 and thep⁻-type column regions 42. It is therefore possible to prevent localconcentration of electric fields in the epitaxial layer 35, making itpossible to reduce the on-resistance of the semiconductor device 31 andto increase the breakdown voltage of the semiconductor device 31.

The n-type column regions 44 are formed of thermal donors. Therefore, ascompared with the related art, it is possible to form a super-junctionstructure in a short period of time and at low cost. Moreover, thesuper-junction structure can be easily incorporated into a MOSFET ofbasic structure without affecting the MOS structure. It is also possibleto prevent variations in specific resistance among the n-type columnregions 44. In addition, it is possible to easily miniaturize the n-typecolumn regions 44, helping to miniaturize the semiconductor device 31.

The annealing for the formation of thermal donors may be performed at atemperature of from 400 degrees C. to 450 degrees C. (the step shown inFIG. 7D). This makes it possible to reduce the specific resistance ofthe n-type column regions 44 and to further reduce the on-resistance.

While certain embodiments of the present disclosure have been describedabove, the present disclosure may be embodied in other forms. Forexample, as shown in FIG. 8, the n-type column regions 10 of thesemiconductor device 1 of the first embodiment may be formed in thedirection of the silicon substrate 2 (in the direction of the rearsurface 11 of the epitaxial layer 5) with respect to the n-type channelregions 7 in a spaced apart relationship with the n-type channel regions7.

The features grasped from the foregoing embodiments may be employed incombination in the respective embodiments. Moreover, the components ofthe respective embodiments may be combined within the scope of thepresent disclosure. In addition, various changes in design may be madewithin the scope of the subject matters defined in the claims.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the disclosures. Indeed, the novel devices and methodsdescribed herein may be embodied in a variety of other forms;furthermore, various omissions, substitutions and changes in the form ofthe embodiments described herein may be made without departing from thespirit of the disclosures. The accompanying claims and their equivalentsare intended to cover such forms or modifications as would fall withinthe scope and spirit of the disclosures.

What is claimed is:
 1. A semiconductor device, comprising: a p-typesemiconductor layer; n-type column regions arranged in a mutuallyspaced-apart relationship along a predetermined direction parallel to afront surface of the semiconductor layer, each of the n-type columnregions formed of thermal donors exhibiting an n-type property; a p-typecolumn region of the semiconductor layer interposed between the n-typecolumn regions adjoining to each other, the n-type column regionsconfigured to form a super-junction structure in the semiconductor layerin cooperation with the p-type column region; a channel region of ann-type or p-type selectively formed in a front surface portion of thesemiconductor layer to make up a portion of the front surface of thesemiconductor layer; a source region selectively formed in a frontsurface portion of the channel region to make up a portion of the frontsurface of the semiconductor layer, a conductivity type of the sourceregion being opposite to that of the channel region; a gate insulatorfilm formed on the front surface of the semiconductor layer; and a gateelectrode formed on the gate insulator film and opposite to the channelregion across the gate insulator film, wherein H⁺ particles areselectively irradiated on a plurality of portions of the semiconductorlayer to form the n-type column regions formed of thermal donors.
 2. Thedevice of claim 1, wherein the n-type column regions have a specificresistance of from 1.0 Ω·cm to 10.0 Ω·cm.
 3. The device of claim 1,wherein the channel region is an n-type and the source region is ap-type, and further comprising: a p-channel MOSFET configured to inducea channel between the p-type source region and the p-type column regionby applying a voltage to the gate electrode.
 4. The device of claim 3,wherein the semiconductor layer includes a p-type base region formed ina direction of a rear surface of the semiconductor layer with respect tothe n-type column regions and the p-type column region so as to extendbelow the n-type column regions and the p-type column region along thepredetermined direction parallel to the front surface of thesemiconductor layer.
 5. The device of claim 1, wherein the channelregion is a p-type and the source region is an n-type, and furthercomprising: an n-channel MOSFET configured to induce a channel betweenthe n-type source region and the n-type column regions by applying avoltage to the gate electrode.
 6. The device of claim 5, wherein thesemiconductor layer includes an n-type base region formed in a directionof a rear surface of the semiconductor layer with respect to the n-typecolumn region and the p-type column region so as to extend below then-type column regions and the p-type column region along thepredetermined direction parallel to the front surface of thesemiconductor layer.
 7. The device of claim 1, wherein the n-type columnregions make contact with the channel region.
 8. The device of claim 1,wherein the n-type column regions includes a region formed on a rearsurface of the p-type semiconductor layer between the channel region andthe n-type column regions spaced apart from the channel region.
 9. Thedevice of claim 1, wherein the selectively irradiating the H⁺ particlesis performed between 5 MeV and 10 MeV.
 10. The device of claim 1,wherein the plurality of irradiated portions of the semiconductor layeris annealed at a temperature of from 400 degrees C. to 450 degrees C.11. The device of claim 1, wherein the n-type column regions formed ofthermal donors are determined by stop positions of the H⁺ particles. 12.The device of claim 1, wherein a range of each of the n-type columnregions formed of thermal donors is determined by controlling anirradiation energy of the H⁺ particles.
 13. The device of claim 1,further comprising a depletion layer formed over an entire interfacebetween each of the n-type column regions and the p-type column regionto extend along the direction of the interface.